1. Field of the Invention
The present invention relates to a semiconductor device having high-density conductive interconnects and, more particularly, to a semiconductor device structure for realizing low electric power consumption and high-speed operation.
2. Description of the Related Art
As a means for accomplishing reductions in semiconductor device size, reductions in electric power consumption, and increases in operation speed, making lower the dielectric constants of interlayer dielectric films has been proposed. One example of this is disclosed in Japanese Patent Laid-Open No. 7650/1988 (Laid-Open Date: Jan. 13, 1988). In particular, a dielectric film between conductive interconnects is made from a low dielectric constant material having a relative dielectric constant smaller than that of dielectric films formed, respectively, over and under the conductive interconnects. Furthermore, in this structure, the dielectric film which is located between the conductive interconnects and has a low relative dielectric constant is in direct contact with the conductive interconnects.
Often, the aforementioned low dielectric constant material consists of a dielectric film to which carbon is added to reduce the dielectric constant down to about 1.5 to 2.5. Alternatively, an organic material such as polyimide, poly-paraxylylene, or polysiloxane is used. Fabrication of semiconductor devices of the interlayer dielectric film structure using these materials has been discussed.
A known method of fabricating a semiconductor device which has an interlayer dielectric film in direct contact with conductive interconnects is described by referring to the schematic cross sections of FIG. 1(a)-l(c). The interlayer dielectric film is made of a low dielectric constant material containing carbon. In FIG. 1(a), the dielectric film, indicated by 13, is formed on a semiconductor substrate 12. Metallization 14 is deposited as a film on the dielectric film 13. The dielectric film 13 is formed SiO.sub.2 to a thickness of about 0.5 .mu.m by CVD, sputtering, or other techniques. The metallization 14 is aluminum (Al) having a small specific resistance and deposited to a thickness of about 0.5 .mu.m.
The state shown in FIG.. 1(b) is obtained by forming a resist pattern by a lithographic method (not shown) and then etching the dielectric film 13 and the metallization 14 at the same time by a dry etching process. In the dry etching process, CCl.sub.4 is normally used to etch the Al. A mixture of CF.sub.4 and H.sub.2 or other material is employed to etch the dielectric film of the SiO.sub.2.
In the state shown in FIG. 1(c), a dielectric film 16 having a relative dielectric constant smaller than that of the dielectric film 13 is buried. This dielectric film 16 consists of polytetrafluoroethylene, polyethylene, or the like.
However, the dielectric film which is used in the prior art techniques and made from a low dielectric constant material containing carbon shows hygroscopicity and so the moisture resistance is poor. Therefore, especially in aluminum interconnects, corrosion takes place, thus deteriorating the reliability of the finished semiconductor device. Furthermore, the plasma resistance is not satisfactory. Especially, the dielectric film is vulnerable to oxygen plasma. Hence, it is difficult to use this dielectric film as an interlayer dielectric film in a semiconductor device.